MC68020 Project phase 1: Free run

Introduction

This is my attempt to write something about my experiments with the MC68020 processor.
It is a desire to finally try to make my own MC68020 board, which ultimately should also have the MC68851 PMMU and the MC68881/68882 FPU to make it complete.
I agree that using a MC68030, MC68040 or MC68060 make my life more easy but that is a different challenge.
I consider the MC68020/MC68851/MC68881 combo this first real intended 32 bit as the original designers intended. I might be wrong of course.
There are several reasons to use a MC68030:

  1. the PMMU is already on board the chip and thus saving one clock cycle for memory access and saving a lot of extra wires
  2. a 256 byte data cache on the chip
  3. support for burst mode

Or use a MC68040 or MC68060

  1. PMMU and FPU on board
  2. larger data and instruction cache
  3. pipelined parallel instruction execution (MC68060)

But… I’m not interrested in performance. I just like to experiment. The MC68020 is just fine.

Free running MC68020

The first step is of course reading the documentation and searching around the internet looking for examples.
A search for MC68020 Homebrew  gave me this interesting video about a free running MC68020.

This is an experiment which is waiting to be repeated. However, since I’m interested in studying the bus cycles of the MC68020 I’ve added some modifications where the socket for the GAL or an ATF750C from Atmel allows the following experiments:

  • Fiddle with DSACK1 and DSACK1
  • Experiment with wait states.
  • Experiment with BERR and HALT both asserted for a few cycles to see the retry mechanism.

Free Run MC68020 CPU connections

D31-D0 areconnected to GND.
BR, BGACK, AVEC, IPL0-IPL2 and CDIS are connected to Vcc.

CPU

After RESET it will start to load the initial SP at address 0x0 and the program counter at address 0x4. Since the data bus is connected to all zeroes, SP and PC will start at address 0x0.

Every instruction fetch will read 0x0 which means:     ORI.B 0,D0

In short, the MC68020 will increase its address lines and executing the same instruction over and over again.
Since the MC68020 always fetches a long word for instruction execution it will read the 2 byte instruction and the 2 byte immediate value using one 32 bit read.

Since the MC68020 uses dynamic bus sizing it will depend on the DSACK0 and DSACK1 how many cycles it will use to fetch the long word. See section 5.2.1 of MC68020UM.
As said, part of the Free Run Experiment will be to be able to play with the DSACK0 and DSACK1 and watch the results on a logic analyzer. The signals which are interesting to watch,will be ECS, OCS, SIZ1 and SIZ0, A0-A3.

Free Run MC68020 CPU Clock
The first part which needs to be created is the clock. The clock usually is a block crystal which generates a TTL level clock. The MC68020 CLK input can directly be fed from such a clock. However, sometimes it is needed to divide the clock using a 74F74 (preferred) or 74LS74. Using a jumper allows to experiment with different clock frequencies. See schematic below.

Free Run MC68020 RESET
The MC68020 needs a proper RESET for at least 512 clocks after power up. For this I used a NE555 timer chip in combination with a 74LS05 and a 1K pull up register. This is needed as the RESET line is a bidirectional open drain line.
Also the HALT line is conected to a 74LS05 and a 1K pull up register! Not having this pull up caused me a day to find out why the board was not working.
See schematic below.

Reset Circuit

Optional GAL
An optional GAL has been added to allow control over DSACK1 and DSACK0, HALT and BERR.
It uses AS, DS, ECS and OCS as an input as well as A13, A12, A11, A10, A9, A9.
GAL

Since I have a bunch of ATF750C from Atmel allows to play with counters without loosing output pins.

 

Address lines BREAKOUT
The CPU A31-A0. FC2-FC0, SIZ1, SIZ0, ECS and OCS are connected to 2 DIL sockets to allow easy access for the probes or otherwise.

address-breakout

One Response to MC68020 Project phase 1: Free run

  1. Pingback: MC68020 Project | avics

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