This is how it looks after assembling the Free Run MC68020.
As can be seen the address lines have been broken out, as some other signals as well.
Now let the experiment start!
DSACK1 and DSACK1 Grounded
According to the MC68020 manual, DSACK1 and DSACK0 determine the size of the bus.
This is visible when connecting a logic analyzer to a few of the signals.
As described in the manual OCS and ECS get asserted when a cylce starts. The CPU requests a long word as indicated by the SIZ0/1 that it expects 4 bytes. A1 and A0 are both negated. DSACK1 and DSACK0 are asserted and the read cycle terminates in 3 cycles. (No wait states). An additional 2 cycles are needed to actually execute the instruction.
Going more in detail, playing with different DSACK0 and DSACK1.
Starting to experiment with an Altera MAX II device. For this one needs level shifters as the device is 3.3V. The device I use is a EPM24T100 ordered from aliexpress.com.
I used level shifters from here. For programming the Altera, use the Quartus Software.
In the this experiment I wanted to see how the MC68020 reacts to different values of DSACK0 and DSACK1 as specified in the User Manual:
Here is the VHDL code:
architecture SEL of led2 is signal dsack0i : std_logic; signal dsack1i : std_logic; begin dsack_logic :process(A, AS) begin if falling_edge(AS) then DSACK0 <= dsack0i; DSACK1 <= dsack1i; end if; end process; with std_logic_vector'(A(5), A(4), A(3)) select (dsack1i,dsack0i) <= std_logic_vector' ("00") when "000", -- 32 bit access std_logic_vector' ("00") when "001", -- 32 bit access std_logic_vector' ("00") when "010", -- 32 bit access std_logic_vector' ("00") when "011", -- 32 bit access std_logic_vector' ("10") when "100", -- 16 bit access std_logic_vector' ("10") when "101", -- 16 bit access std_logic_vector' ("01") when "110", -- 8 bit access std_logic_vector' ("01") when "111" -- 8 bit access ; HALT <= '0'; BERR <= '1'; end architecture SEL;
The result on the logic analyzer: