This is how it looks after assembling the Free Run MC68020.
As can be seen the address lines have been broken out, as some other signals as well.
Now let the experiment start!
DSACK1 and DSACK1 Grounded
According to the MC68020 manual, DSACK1 and DSACK0 determine the size of the bus.
This is visible when connecting a logic analyzer to a few of the signals.
As described in the manual OCS and ECS get asserted when a cylce starts. The CPU requests a long word as indicated by the SIZ0/1 that it expects 4 bytes. A1 and A0 are both negated. DSACK1 and DSACK0 are asserted and the read cycle terminates in 3 cycles. (No wait states). An additional 2 cycles are needed to actually execute the instruction